Hardware Level

Clock Control

class aidatlu.hardware.clock_controller.ClockControl(i2c: I2CCore, io_control: IOControl)

The control class for the Si5344 clock chip. Main purpose is to read/write the clock configuration file to the chip.

check_design_id(hex_str: bool = False) → list

Checks the Chip ID. If the chip is correctly configured the list corresponds

to the data in the clock configuration file between the addresses 0x026B and 0x0272.

Parameters:

hex_str (bool) – Returns the design ID as a list of hex strings. Defaults to False.

Returns:

List of the design ID contains 8 integers or hex strings.

Return type:

list

get_device_version() → int

Get Chip information.

Returns:

The Chip ID.

Return type:

int

parse_clock_conf(file_path: str) → list

reads the clock config file and returns a panda dataframe with two rows Address and Data

The configuration file is produced by Clockbuilder Pro (Silicon Labs).

Parameters:

file_path (str) – File path to the configuration file.

Returns:

2-dim. list, consisting of the address and data values.

Return type:

list

read_clock_register(address: int) → int

Reads register of the clock chip.

Parameters:

address (int) – Address of the register.

Returns:

Integer from the register address.

Return type:

int

write_clock_conf(file_path: str) → None

Writes clock configuration consecutivly in register. This takes a few seconds.

Parameters:

file_path (str) – File path to the clock configuration file.

write_clock_register(address: int, data: int) → None

Write data in specific Clock Chip register.

Parameters:

• address (int) – Destination register.

• data (int) – Data to be written in address.

DAC Control

class aidatlu.hardware.dac_controller.DacControl(i2c: I2CCore, int_ref: bool = False)

Control class for the three AD5665R. One controls the PMT control power (pwr_dac). Two set the trigger input thresholds (dac_1, dac_2). Each AD5665R has four parallel outputs.

set_threshold(trigger_channel: int, threshold_voltage: float, ref_v: float = 1.3) → None

Sets the Threshold voltage for the trigger input channel. Use channel = 7 to set threshold for all channels.

Parameters:

• trigger_channel (int) – Trigger input channel. From 1 to 7, where 7 controls all input channels.

• threshold_voltage (float) – Threshold voltage in volt.

• ref_v (float) – Reference voltage of the DAC. Defaults to the external reference voltage 1.3 V.

set_voltage(pmt_channel: int, voltage: float) → None

Sets given PMT DAC to given output voltage.

Parameters:

• pmt_channel (int) – DAC channel for the PMT from 1 to 5, where channel 5 sets the voltage of all PMT channels.

• voltage (float) – DAC output voltage

DUT Control

class aidatlu.hardware.dut_controller.DUTLogic(i2c: I2CCore)

get_dut_ignore_busy() → int

Reads the content in the register ‘IgnoreDUTBusyR’.

Returns:

Integer content of the register.

Return type:

int

get_dut_mask() → int

Reads the contend in the register ‘DUTMaskR’.

Returns:

Integer content of the register.

Return type:

int

get_dut_mask_mode() → int

Reads the contend in the register ‘DUTInterfaceModeR’.

Returns:

Integer content of the register.

Return type:

int

get_dut_mask_mode_modifier() → int

Reads the content in the register ‘DUTInterfaceModeModifierR’.

Returns:

Integer content of the register.

Return type:

int

set_dut_ignore_busy(channels: int | str) → None

If set the TLU ignores the BUSY signal from a DUT in AIDA mode.

Channels consists of a 4-bit WORD describing the DUT interfaces. With DUT interface 1 = bit 0, interface 2 = bit 1, interface 3 = bit 2 and interface 4 = bit 3. #TODO not sure if this is true here. No answers in documentation.

Parameters:

channels (int | str) – _description_#TODO

set_dut_mask(enable: int | str) → None

Enables HDMI Outputs the enable is here an 4-bit WORD as integer or binary string to enable each HDMI channel.

With HDMI channel 1 = bit 0, channel 2 = bit 2, channel 3 = bit 3 and channel 4 = bit 4. E.q. 0b0001 or ‘0001’ enables HDMI channel 1, ‘0011’ enables channel 1 and 2 and so on.

Parameters:

value (int | str) – 4-bit WORD to enable the the HDMI outputs. Can be an integer or binary string.

set_dut_mask_mode(mode: int | str) → None

Sets the DUT interface mode. Mode consists of one 8-bit WORD or more specific 4 2-bit WORDs.

Each 2-bit WORD corresponds to one HDMI output and its mode. With HDMI channel 1 = bit 0 and 1, channel 2 = bit 2 and 3, channel 3 = bit 4 and 5 and channel 4 = bit 6 and 7. The mode is set with X0 = EUDET and X1 = AIDA. #TODO They mention the leading bit X can be used for future modes. Is this still up to date? E.q. 0b00000011 sets HDMI channel 1 to AIDA mode and channels 2,3 and 4 to EUDET.

Parameters:

mode (int | str) – 8-bit WORD to set the mode for each DUT. Can be an integer or binary string.

set_dut_mask_mode_modifier(value: int) → None

#TODO Only affects the EUDET mode of operation, looks like some special EUDET configuration.

Parameters:

value (int) – _description_ #TODO

I2C

class aidatlu.hardware.i2c.I2CCore(hw_int)

read_register(register: str) → int

register: str Name of node in address file

write_register(register: str, value: int) → None

register: str Name of node in address file value: int Value to be written

IO Expander Control

class aidatlu.hardware.ioexpander_controller.IOControl(i2c: I2CCore)

Main class for the control of the IO expander PCA9539PW. Four I/O expanders are in use, two for the 11 front panel LEDs. and two for the HDMI DUT interfaces.

all_off() → None

Turn off all LEDs

all_on(color: str = 'w') → None

Set all LEDs to same color

Parameters:

color (str, optional) – Color code [white: “w”, red: “r”, green: “g”, blue: “b”] Defaults to “w”.

clock_hdmi_output(hdmi_channel: int, clock_source: str) → None

Enables the Clock output for one HDMI channel.

Valid Clock sources are Si5453 clock chip ‘chip’ and FPGA ‘fpga’. #TODO does FPGA work?

Parameters:

• hdmi_channel (int) – HDMI channels from 1 to 4

• clock_source (str) – Clock source valid options are ‘off’, ‘chip’ and ‘fpga’.

clock_lemo_output(enable: bool = True) → None

Enables the clock LEMO output. #TODO only with ~40MHz default clock

Parameters:

enable (bool, optional) – Enable clock LEMO output. Defaults to True.

configure_hdmi(hdmi_channel: int, enable: int | str) → None

This enables the pins of one HDMI channel as input (0) or output (1).

Enable is a 4-bit WORD for each pin as integer or binary string. With CONT = bit 0, SPARE = bit 1, TRIG = bit 2 and BUSY = bit 3. E.q. 0b0111 or ‘0111’ sets CONT, SPARE and TRIGGER as outputs and BUSY as input. ‘1100’ sets CONT and SPARE as input and BUSY and TRIG as output. The clock runs with the separate function: clock_hdmi_output.

Parameters:

• hdmi_num (int) – HDMI channels from 1 to 4

• enable (int | str, optional) – 4-bit WORD to enable the 4 pins on the HDMI output. Can be an integer or binary string.

init_led_expander() → None

Initialize LED expanders

init_output_expander() → None

Initialize output expanders

switch_led(led_id: int, color: str = 'off') → None

changes LED with led_id to specific color

Parameters:

• led_id (int) – ID for the 11 LEDs, led_id has to be between 1 and 11

• color (str, optional) – Color code [white: “w”, red: “r”, green: “g”, blue: “b”, off: “off”] for Clock LED only [red: “r”, green: “g”, off: “off”]. Defaults to “off”.

test_leds(single=True) → None

Test the 11 LEDs

Parameters:

single (bool, optional) – Test all possible RGB combinations for all LEDs. Defaults to True.

Trigger Control

class aidatlu.hardware.trigger_controller.TriggerLogic(i2c: I2CCore)

get_internal_trigger_frequency() → int

Reads the internal trigger frequency from the register.

Returns:

Frequency in Hz

Return type:

int

get_post_veto_trigger() → int

Gets the number of triggers recorded in the TLU after the veto is applied

get_pre_veto_trigger() → int

Number of triggers recorded in the TLU before the veto is applied.

get_pulse_delay_pack() → int

Get packed word describing the input pulse stretch.

get_pulse_stretch_pack() → int

Get packed word describing the input pulse stretch.

get_trigger_mask() → int

Retrieves the trigger logic words from the registers. The trigger pattern represents one of the 64 possible logic combinations.

get_trigger_veto() → bool

Reads the trigger veto from the register.

set_internal_trigger_frequency(frequency: int) → None

Sets the internal trigger frequency. The maximum allowed Frequency is 160 MHz.

Parameters:

frequency (int) – Frequency in Hz

set_pulse_delay_pack(vector: list) → None

Delay word for trigger pulses. Each element of the input vector is delayed by N clock cycles.

The vector is packed into a single word.

Parameters:

vector (list) – A vector containing six integers. Each trigger input is delayed by the integer number of clock cycles.

set_pulse_stretch_pack(vector: list) → None

Stretch word for trigger pulses. Each element of the input vector is stretched by N clock cycles.

The input vector should have 6 elements for the different inputs. The vector is packed into a single word.

Parameters:

vector (list) – A vector containing six integers. Each trigger input is stretched by the integer number of clock cycles.

set_trigger_mask(mask_high: int, mask_low: int) → None

Sets the trigger logic. Each of the 64 possible combination is divided into two 32-bit words mask high and mask low.

Parameters:

• mask_high (int) – The most significant 32-bit word generated from the trigger configuration.

• mask_low (int) – The least significant 32-bit word generated from the trigger configuration.

set_trigger_mask_from_full_word(value: int) → None

Sets the trigger logic. Each of the 64 possible combination is divided into two 32-bit words mask high and mask low.

Parameters:

value (int) – Sets trigger logic from trigger logic combination word.

set_trigger_polarity(value: int) → int

Sets if the TLU triggers on rising or falling edge.

Parameters:

value (int) – 1 triggers on falling, 0 on rising. #TODO not tested

set_trigger_veto(veto: bool) → None

Enables or disables new trigger. This can be used to reset the procession of new triggers. :param veto: Sets a veto to the trigger logic of the tlu. :type veto: bool