Configuration#

The AIDA-2020 TLU is configured using a yaml file (tlu_configuration.yaml). In the following, the possible configuration parameters and settings are briefly explained.

Internal Trigger Generation (internal_trigger)#

The setting internal trigger allows the TLU to generate a trigger internally with a given frequency. To disable the generation of internal triggers set this frequency to zero.

DUT Module (dut_module)#

The DUT module configures the individual DUT interfaces. Where each interface can be set to one operating mode. The possible modes are ‘aida’, ‘aidatrig’ and ‘eudet’. With ‘aidatrig’ the AIDA mode with additional trigger number. And ‘aida’ or ‘eudet’ the AIDA or EUDET operating modes. It is important to note that only working DUT devices should be enabled. One not properly working DUT can block the TLU from sending out triggers (especially in EUDET mode).

Trigger Inputs (trigger_inputs)#

Multiple settings of the trigger inputs are configurable. This includes trigger input thresholds, trigger logic, trigger polarity and trigger signal shaping.

The threshold for each trigger input can be tuned individually between [-1.3; 1.3] V.

Another setting controls the trigger input logic. Each trigger input can have one of three settings. The input can act as ‘active’, ‘veto’ or ‘do not care’. Between each trigger input, there is also the possibility to set ‘AND’ or ‘OR’. A desired trigger configuration is set with the use of the Python bitwise operators. These operators are used in conjunction with the input channels CH1-CH6 and interpreted as a literal logic expression. For example “(CH1 & ~CH2) & (CH3 | CH4 | CH5 | CH6)” produces a valid trigger, when CH1 and not CH2 triggers and when one of CH3, CH4, CH5 or CH6 triggers. An input channel that is not explicitly set to ‘veto’ or ‘enabled’ is automatically set to ‘do not care’.

Trigger polarity controls if the TLU should trigger on a rising (0) or falling (1) edge of an incoming trigger signal.

Each trigger input signal can be delayed and stretched by a given number of clock cycles. This is set with a list containing the number of clock cycles for every different trigger input. This value is written in a 5-bit register so the maximum stretch or delay in clock cycles is 32. One should stretch each used trigger input signal at least by 1 to prevent the generation of incomplete triggers.

Clock LEMO (clock_lemo)#

The clock LEMO setting enables or disables the clock LEMO output. Set this to ‘True’ or ‘False’.

PMT Power (pmt_control)#

Set the PMT control voltage. The possible range is between [0; 1] V.

Data Handling and Online Monitor#

Two settings concern the data handling. The creation of raw and interpreted data files. At last, the ZMQ connection can be configured.

Stop Conditions#

Two optional stop conditions can be set in tlu_configuration.yaml. The maximum number of trigger events (max_trigger_number, e.g. max_trigger_number: 1000000) and a timeout in seconds (timeout, e.g. timeout: 100) can be set. These configurations are not included by default in the tlu_configuration file, so add them manually if needed.

Configuration File#

internal_trigger: #Generate TLU internal trigger with given rate in Hz
  internal_trigger_rate: 10000

dut_module:
  dut_1:
    mode: 'aida' # 'aida', 'aidatrig', 'eudet', 'any'
  dut_2:
    mode: 'aida'   # 'aida', 'aidatrig', 'eudet', 'any'
  dut_3:
    mode: 'eudet'   # 'aida', 'aidatrig', 'eudet', 'any'
  dut_4:
    mode: 'off'   # 'aida', 'aidatrig', 'eudet', 'any'

trigger_inputs: #threshold voltages for the trigger inputs in V.
  threshold:
    threshold_1: -0.1
    threshold_2: -0.1
    threshold_3: -0.1
    threshold_4: -0.1
    threshold_5: -0.1
    threshold_6: -0.1

  # Trigger Logic configuration accept a python expression for the trigger inputs.
  # The logic is set by using the variables for the input channels 'CH1', 'CH2', 'CH3', 'CH4', 'CH5' and 'CH6'
  # and the Python bitwise operators AND: '&', OR: '|', NOT: '~' and so on. Dont forget to use brackets...
  trigger_inputs_logic: CH2 & CH4

  trigger_polarity: #TLU triggers on rising (0) or falling (1) edge
    polarity: 1

  trigger_signal_shape: #Stretches and delays each trigger input signal for an number of clock cycles,
    stretch: [2, 2, 2, 2, 2, 2]
    delay: [0, 0, 0, 0, 0, 0]

clock_lemo:
  enable_clock_lemo_output: True
pmt_control:
  #PMT control voltages in V
  pmt_1: 0.8
  pmt_2: 0.8
  pmt_3: 0
  pmt_4: 0

#Save data and generate interpreted data from the raw data set. Set to 'True' or 'False'.
save_data: True
output_data_path:

#zmq connection leave it blank or set to 'off' if not needed
zmq_connection: 'off' #"tcp://127.0.0.1:6500"

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