Configuration#
Configuration#
The AIDA-2020 TLU is configured using a yaml file (tlu_configuration.yaml). In the following, the possible configuration parameters and settings are briefly explained.
Internal Trigger Generation (internal_trigger)#
The setting internal trigger allows the TLU to generate a trigger internally with a given frequency. To disable the generation of internal triggers set this frequency to zero.
DUT Module (dut_module)#
The DUT module configures the individual DUT interfaces. Where each interface can be set to one operating mode. The possible modes are ‘aida’, ‘aidatrig’ and ‘eudet’. With ‘aidatrig’ the AIDA mode with additional trigger number. And ‘aida’ or ‘eudet’ the AIDA or EUDET operating modes. It is important to note that only working DUT devices should be enabled. One not properly working DUT can block the TLU from sending out triggers (especially in EUDET mode).
Trigger Inputs (trigger_inputs)#
Multiple settings of the trigger inputs are configurable. This includes trigger input thresholds, trigger logic, trigger polarity and trigger signal shaping.
The threshold for each trigger input can be tuned individually between [-1.3; 1.3] V.
Another setting controls the trigger input logic. Each trigger input can have one of three settings. The input can act as ‘active’, ‘veto’ or ‘do not care’. Between each trigger input, there is also the possibility to set ‘AND’ or ‘OR’. A desired trigger configuration is set with the use of the Python boolean operators. These operators are used in conjunction with the input channels CH1-CH6 and interpreted as a literal logic expression. For example “(CH1 & (not CH2)) and (CH3 or CH4 or CH5 or CH6)” produces a valid trigger, when CH1 and not CH2 triggers and when one of CH3, CH4, CH5 or CH6 triggers. An input channel that is not explicitly set to ‘veto’ or ‘enabled’ is automatically set to ‘do not care’.
TLU can trigger on a rising or falling edge. Trigger polarity is set using a string or boolean, ‘rising’ corresponds to false (0) and ‘falling’ to true (1)
Each trigger input signal can be delayed and stretched by a given number of clock cycles. This is set with a list containing the number of clock cycles for every different trigger input. This value is written in a 5-bit register so the maximum stretch or delay in clock cycles is 32. One should stretch each used trigger input signal at least by 1 to prevent the generation of incomplete triggers.
Clock LEMO (clock_lemo)#
The clock LEMO setting enables or disables the clock LEMO output. Set this to ‘True’ or ‘False’.
PMT Power (pmt_control)#
Set the PMT control voltage. The possible range is between [0; 1] V.
Data Handling and Online Monitor#
Two settings concern the data handling. The creation of raw and interpreted data files. At last, the ZMQ connection can be configured.
Stop Conditions#
Two optional stop conditions can be set in tlu_configuration.yaml. The maximum number of trigger events (max_trigger_number, e.g. max_trigger_number: 1000000) and a timeout in seconds (timeout, e.g. timeout: 100) can be set. These configurations are not included by default in the tlu_configuration file, so add them manually if needed.
Configuration with yaml#
Example configuration using the yaml file format.
# Generate TLU internal trigger with given rate in Hz
internal_trigger_rate: 0
# Set operating mode of the DUT, supported are three operating modes 'aida', 'aidatrig' and 'eudet'
# Set unused DUT interfaces to off, false or None
dut_module:
dut_1:
mode: aida
dut_2:
mode: aida
dut_3:
mode: eudet
dut_4:
mode: off
trigger_inputs:
# Threshold voltages for the trigger inputs in V.
threshold:
threshold_1: -0.1
threshold_2: -0.1
threshold_3: -0.1
threshold_4: -0.1
threshold_5: -0.1
threshold_6: -0.1
# Trigger Logic configuration accept a python expression for the trigger inputs.
# The logic is set by using the variables for the input channels 'CH1', 'CH2', 'CH3', 'CH4', 'CH5' and 'CH6'
# and the Python logic operators: 'and', 'or', 'not' and so on. Dont forget to use brackets...
trigger_inputs_logic: 'CH1 and CH2'
# TLU can trigger on a rising or falling edge. Trigger polarity is set using a string or boolean,
# 'rising' corresponds to false and 'falling' to true
trigger_polarity: falling
# Stretches and delays each trigger input signal for an number of clock cycles (corresponds to 6.25ns steps),
# The stretch and delay of all inputs is given as a list,
# each entry corresponding to an individual trigger input.
trigger_signal_shape:
stretch: [2, 2, 2, 2, 2, 2]
delay: [0, 0, 0, 0, 0, 0]
# Enable the LEMO clock output using a boolean.
enable_clock_lemo_output: True
# Set the four PMT control voltages in V
pmt_control:
pmt_1: 0.8
pmt_2: 0.8
pmt_3: 0
pmt_4: 0
# Save and generate interpreted data from the raw data set. Set to 'True' or 'False'.
# If no specific output path is provided, the data is saved in the default output data path (aidatlu/aidatlu/tlu_data).
save_data: True
output_data_path:
# zmq connection for status messages, leave it blank or set to off if not needed
zmq_connection: off #"tcp://:7500"
# Optional stop conditions these can be by timeout in seconds or a maximum output trigger number.
max_trigger_number: None
timeout: None
Configuration with toml#
The TLU can be configured using the toml file format. An example can be found below.
internal_trigger_rate = 100000
dut_interfaces = ['aida', 'eudet', 'aidatrig', 'off']
trigger_threshold = [-0.1, -0.2, -0.3, -0.4, -0.5, -0.6]
trigger_inputs_logic = '(CH1 and (not CH2) and (not CH3) and (not CH4) and (CH5) and (not CH6))'
trigger_polarity = 'falling'
trigger_signal_stretch = [2, 2, 3, 2, 2, 2]
trigger_signal_delay = [0, 1, 0, 0, 3, 0]
enable_clock_lemo_output = 'True'
pmt_power = [0.8, 0.8, 0, -0.2]
save_data = 'True'
output_data_path = 'aidatlu/test/fixtures/test_output_data/'
zmq_connection = 'False'
# Optional stop conditions can also be added to the configuration.
# These can be by timeout in seconds or a maximum output trigger number.
max_trigger_number = 'None'
timeout = 5